module IFU #(PC_RST = 64'h0000_0000_8000_0000) (
  input clk,
  input rst,
  input [63:0] dnpc,
  output reg [63:0] pc,
  output [1:0] MemOp
);
initial begin
    pc = 64'h80000000;
end
  assign MemOp = 2'b01;
  always @(posedge clk) begin
    if(rst) begin
      pc <= PC_RST;
    end
    else begin
      pc <= dnpc;
    end
  end

endmodule